package memlib

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Visibility
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Type Members

  1. class ConfWriter extends AnyRef
  2. case class Config(pin: Pin, source: Source, top: Top) extends Product with Serializable
  3. class CreateMemoryAnnotations extends Transform
  4. case class DefAnnotatedMemory(info: Info, name: String, dataType: Type, depth: Int, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String], readUnderWrite: Option[String], maskGran: Option[BigInt], memRef: Option[(String, String)]) extends Statement with IsDeclaration with Product with Serializable
  5. class InferReadWrite extends Transform with SeqTransformBased
  6. case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] with Product with Serializable

    A component, e.g.

    A component, e.g. register etc. Must be declared only once under the TopAnnotation

  7. sealed trait PassOption extends AnyRef
  8. case class Pin(name: String) extends Product with Serializable
  9. case class PinAnnotation(pins: Seq[String]) extends NoTargetAnnotation with Product with Serializable

    Annotates the name of the pins to add for WiringTransform

  10. class ReplSeqMem extends Transform
  11. case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation with Product with Serializable
  12. class ReplaceMemMacros extends Transform

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.

  13. class ResolveMemoryReference extends Transform

    Resolves annotation ref to memories that exactly match (except name) another memory

  14. class SimpleMidTransform extends SimpleTransform
  15. class SimpleTransform extends Transform
  16. case class Source(name: String, module: String) extends Product with Serializable
  17. case class Top(name: String) extends Product with Serializable
  18. class YamlFileReader extends AnyRef
  19. class YamlFileWriter extends AnyRef

Value Members

  1. object AnalysisUtils
  2. object CustomYAMLProtocol extends DefaultYamlProtocol
  3. object InferReadWriteAnnotation extends NoTargetAnnotation with Product with Serializable
  4. object InferReadWritePass extends Transform with Pass
  5. object InputConfigFileName extends PassOption with Product with Serializable
  6. object MemTransformUtils
  7. object OutputConfigFileName extends PassOption with Product with Serializable
  8. object PassCircuitName extends PassOption with Product with Serializable
  9. object PassConfigUtil
  10. object PassModuleName extends PassOption with Product with Serializable
  11. object RenameAnnotatedMemoryPorts extends Transform with Pass

    Changes memory port names to standard port names (i.e.

    Changes memory port names to standard port names (i.e. RW0 instead T_408)

  12. object ReplSeqMemAnnotation extends Serializable
  13. object ResolveMaskGranularity extends Transform with Pass

    Determines if a write mask is needed (wmode/en and wmask are equivalent).

    Determines if a write mask is needed (wmode/en and wmask are equivalent). Populates the maskGran field of DefAnnotatedMemory Annotations:

    • maskGran = (dataType size) / (number of mask bits)
      • i.e. 1 if bitmask, 8 if bytemask, absent for no mask TODO(shunshou): Add floorplan info?
  14. object ToMemIR extends Transform with Pass

    Annotates sequential memories that are candidates for macro replacement.

    Annotates sequential memories that are candidates for macro replacement. Requirements for macro replacement:

    • read latency and write latency of one
    • only one readwrite port or write port
    • zero or one read port
  15. object VerilogMemDelays extends Transform with Pass

    This pass generates delay reigsters for memories for verilog

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