Value Members

1.  object CInferMDir extends Transform with Pass
2.  object CInferTypes extends Transform with Pass
3.  object CheckChirrtl extends Transform with Pass
4.  object CheckGenders extends Transform with Pass
5.  object CheckHighForm extends Transform with Pass
6.  object CheckInitialization extends Transform with Pass

   Reports errors for any references that are not fully initialized

   Reports errors for any references that are not fully initialized

   Note

   Assumes single connection (ie. no last connect semantics)

   ,

   This pass looks for firrtl.WVoids left behind by ExpandWhens

7.  object CheckTypes extends Transform with Pass
8.  object CheckWidths extends Transform with Pass
9.  object CommonSubexpressionElimination extends Transform with Pass
10.  object ConvertFixedToSInt extends Transform with Pass

    Replaces FixedType with SIntType, and correctly aligns all binary points

11.  object DeadCodeElimination extends Transform
12.  object ExpandConnects extends Transform with Pass
13.  object ExpandWhens extends Transform with Pass

    Expand Whens

    Expand Whens

    This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches

    Note

    Assumes all references are declared

    ,

    Assumes bulk connects and isInvalids have been expanded

14.  object InferTypes extends Transform with Pass
15.  object InferWidths extends Transform with Pass
16.  object Legalize extends Transform with Pass
17.  object LowerTypes extends Transform

    Removes all aggregate types from a firrtl.ir.Circuit

    Removes all aggregate types from a firrtl.ir.Circuit

    Example:

    1. wire foo : { a : UInt<32>, b : UInt<16> }

       lowers to

       wire foo_a : UInt<32>
       wire foo_b : UInt<16>

    Note

    Assumes firrtl.ir.Connects and firrtl.ir.IsInvalids only operate on firrtl.ir.Expressions of ground type

    ,

    Assumes firrtl.ir.SubAccesses have been removed

18.  object MemPortUtils
19.  object PadWidths extends Transform with Pass
20.  object PullMuxes extends Transform with Pass
21.  object RemoveAccesses extends Transform with Pass

    Removes all firrtl.WSubAccess from circuit

22.  object RemoveCHIRRTL extends Transform
23.  object RemoveEmpty extends Transform with Pass
24.  object RemoveValidIf extends Transform with Pass

    Remove ValidIf and replace IsInvalid with a connection to zero

25.  object ReplaceAccesses extends Transform with Pass

    Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop

26.  object ResolveGenders extends Transform with Pass
27.  object ResolveKinds extends Transform with Pass
28.  object SplitExpressions extends Transform with Pass
29.  object ToWorkingIR extends Transform with Pass
30.  object Uniquify extends Transform

    Resolve name collisions that would occur in LowerTypes

    Resolve name collisions that would occur in LowerTypes

    Example:

    1. wire a = { b, c }[2]
       wire a_0

       This lowers to:

       wire a__0_b
       wire a__0_c
       wire a__1_b
       wire a__1_c
       wire a_0

       There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a

    Note

    Must be run after InferTypes because ir.DefNodes need type

31.  object VerilogModulusCleanup extends Transform with Pass

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))

    This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes

32.  object VerilogPrep extends Transform with Pass

    Makes changes to the Firrtl AST to make Verilog emission easier

    Makes changes to the Firrtl AST to make Verilog emission easier

    - For each instance, adds wires to connect to each port

    • Note that no Namespace is required because Uniquify ensures that there will be no collisions with the lowered names of instance ports - Also removes Attaches where a single Port OR Wire connects to 1 or more instance ports
    • These are expressed in the portCons of WDefInstConnectors

    Note

    The result of this pass is NOT legal Firrtl

33.  object VerilogRename extends Transform with Pass
34.  object ZeroWidth extends Transform
35.  object createMask
36.  object toBitMask

    Given a mask, return a bitmask corresponding to the desired datatype.

    Given a mask, return a bitmask corresponding to the desired datatype. Requirements:

    • The mask type and datatype must be equivalent, except any ground type in datatype must be matched by a 1-bit wide UIntType.
    • The mask must be a reference, subfield, or subindex The bitmask is a series of concatenations of the single mask bit over the length of the corresponding ground type, e.g.:

    wire mask: {x: UInt<1>, y: UInt<1>}
    wire data: {x: UInt<2>, y: SInt<2>}
    // this would return:
    cat(cat(mask.x, mask.x), cat(mask.y, mask.y))