c

firrtl.ir

ExtModule

case class ExtModule(info: Info, name: String, ports: Seq[Port], defname: String, params: Seq[Param]) extends DefModule with Product with Serializable

External Module

Generally used for Verilog black boxes

defname

Defined name of the external module (ie. the name Firrtl will emit)

Linear Supertypes
Serializable, Serializable, Product, Equals, DefModule, IsDeclaration, HasInfo, HasName, FirrtlNode, AnyRef, Any
Type Hierarchy
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. ExtModule
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. DefModule
  7. IsDeclaration
  8. HasInfo
  9. HasName
  10. FirrtlNode
  11. AnyRef
  12. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new ExtModule(info: Info, name: String, ports: Seq[Port], defname: String, params: Seq[Param])

    defname

    Defined name of the external module (ie. the name Firrtl will emit)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )
  6. val defname: String
  7. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  8. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  9. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  10. val info: Info
    Definition Classes
    ExtModule → DefModule → HasInfo
  11. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  12. def mapInfo(f: (Info) ⇒ Info): DefModule
    Definition Classes
    ExtModule → DefModule
  13. def mapPort(f: (Port) ⇒ Port): DefModule
    Definition Classes
    ExtModule → DefModule
  14. def mapStmt(f: (Statement) ⇒ Statement): DefModule
    Definition Classes
    ExtModule → DefModule
  15. def mapString(f: (String) ⇒ String): DefModule
    Definition Classes
    ExtModule → DefModule
  16. val name: String
    Definition Classes
    ExtModule → DefModule → HasName
  17. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  18. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  19. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  20. val params: Seq[Param]
  21. val ports: Seq[Port]
    Definition Classes
    ExtModule → DefModule
  22. def serialize: String
    Definition Classes
    ExtModule → FirrtlNode
  23. def serializeHeader(tpe: String): String
    Attributes
    protected
    Definition Classes
    DefModule
  24. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  25. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  26. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  27. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from DefModule

Inherited from IsDeclaration

Inherited from HasInfo

Inherited from HasName

Inherited from FirrtlNode

Inherited from AnyRef

Inherited from Any

Ungrouped