class VerilogEmitter extends SeqTransform with Emitter
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Instance Constructors
- new VerilogEmitter()
Type Members
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class
VerilogRender extends AnyRef
Used by getRenderer, it has machinery to produce verilog from IR.
Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.
Value Members
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final
def
!=(arg0: Any): Boolean
- Definition Classes
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final
def
##(): Int
- Definition Classes
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final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def AND(e1: WrappedExpression, e2: WrappedExpression): Expression
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final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
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def
clone(): AnyRef
- Attributes
- protected[java.lang]
- Definition Classes
- AnyRef
- Annotations
- @native() @throws( ... )
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def
emit(state: CircuitState, writer: Writer): Unit
- Definition Classes
- VerilogEmitter → Emitter
- def emit(x: Any, top: Int)(implicit w: Writer): Unit
- def emit(x: Any)(implicit w: Writer): Unit
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final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
execute(state: CircuitState): CircuitState
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
- Definition Classes
- VerilogEmitter → SeqTransform → Transform
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def
finalize(): Unit
- Attributes
- protected[java.lang]
- Definition Classes
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- Annotations
- @throws( classOf[java.lang.Throwable] )
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final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
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def
getRenderer(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer): VerilogRender
Gets a reference to a verilog renderer.
Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.
- m
the start module
- moduleMap
a way of finding other modules
- writer
where rendering will be placed
- returns
the render reference
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def
hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
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def
inputForm: LowForm.type
The firrtl.CircuitForm that this transform requires to operate on
The firrtl.CircuitForm that this transform requires to operate on
- Definition Classes
- VerilogEmitter → Transform
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final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
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val
logger: Logger
- Definition Classes
- LazyLogging
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def
name: String
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
- Definition Classes
- Transform
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final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
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final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
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final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
- def op_stream(doprim: DoPrim): Seq[Any]
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def
outputForm: LowForm.type
The firrtl.CircuitForm that this transform outputs
The firrtl.CircuitForm that this transform outputs
- Definition Classes
- VerilogEmitter → Transform
- def remove_root(ex: Expression): Expression
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final
def
runTransform(state: CircuitState): CircuitState
Perform the transform and update annotations.
Perform the transform and update annotations.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
- Definition Classes
- Transform
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def
runTransforms(state: CircuitState): CircuitState
- Attributes
- protected
- Definition Classes
- SeqTransformBased
- def stringify(tpe: GroundType): String
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def
stringify(param: Param): String
Turn Params into Verilog Strings
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final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
- val tab: String
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def
toString(): String
- Definition Classes
- AnyRef → Any
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def
transforms: Seq[Transform]
Preamble for every emitted Verilog file
Preamble for every emitted Verilog file
- Definition Classes
- VerilogEmitter → SeqTransformBased
- def v_print(e: Expression)(implicit w: Writer): Unit
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final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @throws( ... )
- def wref(n: String, t: Type): WRef
Deprecated Value Members
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final
def
getMyAnnotations(state: CircuitState): Seq[Annotation]
Convenience method to get annotations relevant to this Transform
Convenience method to get annotations relevant to this Transform
- state
The CircuitState form which to extract annotations
- returns
A collection of annotations
- Definition Classes
- Transform
- Annotations
- @deprecated
- Deprecated
(Since version 1.1) Just collect the actual Annotation types the transform wants
This is the documentation for Firrtl.