Packages

c

firrtl.VerilogEmitter

VerilogRender

class VerilogRender extends AnyRef

Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.

Linear Supertypes
AnyRef, Any
Type Hierarchy
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. VerilogRender
  2. AnyRef
  3. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)

    m

    the start module

    moduleMap

    a map of modules so submodules can be discovered

    writer

    where rendered information is placed.

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def assign(e: Expression, value: Expression, info: Info): Unit
  6. val assigns: ArrayBuffer[Seq[Any]]
  7. val at_clock: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
  8. val attachAliases: ArrayBuffer[Seq[Any]]
  9. val attachSynAssigns: ArrayBuffer[Seq[Any]]
  10. def build_netlist(s: Statement): Statement
  11. def build_ports(): Unit
  12. def build_streams(s: Statement): Statement
  13. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )
  14. def declare(b: String, n: String, t: Type, info: Info): ArrayBuffer[Seq[Any]]
  15. val declares: ArrayBuffer[Seq[Any]]
  16. def emitVerilogBind(overrideName: String, body: String): DefModule

    This emits a verilog module that can be bound to a module defined in chisel.

    This emits a verilog module that can be bound to a module defined in chisel. It uses the same machinery as the general emitter in order to insure that parameters signature is exactly the same as the module being bound to

    overrideName

    Override the module name

    body

    the body of the bind module

    returns

    A module constructed from the body

  17. def emit_streams(): Unit
  18. def emit_verilog(): DefModule

    The standard verilog emitter, wraps up everything into the verilog

  19. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  20. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  21. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  22. def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression, info: Info): ArrayBuffer[Seq[Any]]
  23. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  24. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  25. def initialize(e: Expression): ArrayBuffer[Seq[Any]]
  26. def initialize_mem(s: DefMemory): Unit
  27. val initials: ArrayBuffer[Seq[Any]]
  28. val instdeclares: ArrayBuffer[Seq[Any]]
  29. def invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]
  30. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  31. val namespace: Namespace
  32. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  33. val netlist: LinkedHashMap[WrappedExpression, Expression]
  34. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  35. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  36. val portdefs: ArrayBuffer[Seq[Any]]
  37. def printf(str: StringLit, args: Seq[Expression]): Seq[Any]
  38. def rand_string(t: Type): Seq[Any]
  39. def regUpdate(r: Expression, clk: Expression): ArrayBuffer[Seq[Any]]
  40. def simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]
  41. val simulates: ArrayBuffer[Seq[Any]]
  42. def stop(ret: Int): Seq[Any]
  43. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  44. def toString(): String
    Definition Classes
    AnyRef → Any
  45. def update(e: Expression, value: Expression, clk: Expression, en: Expression, info: Info): ArrayBuffer[Seq[Any]]
  46. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  47. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  48. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )

Inherited from AnyRef

Inherited from Any

Ungrouped